1. Field of the Invention
The present invention relates to a solid-state imaging apparatus.
2. Description of the Related Art
The solid-state imaging apparatus in recent years is used in various equipment such as a digital camera, a digital video camera and a mobile telephone, and is required to have higher functionalities. There is a strong request for a greater number of pixels in particular, and it is essential to downsize the pixel and the read out circuit for reading the signal of the pixel. When downsizing the read out circuit which is configured to have an amplifier circuit using a feedback type capacitor in every column, it becomes necessary to reduce the capacitance values. In this case, an offset increases which originates in injected charges due to the charge injection which occurs when the amplifier circuit is initialized. The following method is known as a method of reducing the charge injection and a clock feed-through which occur when the amplifier circuit using the feedback type capacitor is initialized.
A dummy transistor which short-circuits its source and its drain is connected between a reset switch and a negative input terminal of an inversion amplifier circuit. At this time, a pulse which is applied to the gate of the dummy transistor is an inversion pulse of the pulse which controls the reset switch. This pulse makes the charge injection and the clock feed-through to be absorbed in the channel of the dummy transistor.
As an example of the above described technique, Japanese Patent Application Laid-Open No. H08-204509 is known. However, the above described offset cancellation method has a possibility that the offset cannot be reduced to a designed value due to the variation in the manufacture of the transistor, for instance.